1. Field of the Invention
Generally, the present invention relates to the fabrication of highly sophisticated integrated circuits including transistor elements with minimum feature sizes of 0.1 μm and less, and, more particularly, to highly capacitive gate structures including a dielectric with a thickness of an oxide capacitance equivalent thickness of 2 nm and less.
2. Description of the Related Art
In modem integrated circuits, minimum feature sizes are steadily decreasing and presently approach 0.1 μm with the prospect of 0.08 μm in the near future. Of the many problems encountered in steadily decreasing feature sizes, one essential issue has to be resolved to allow the further scaling of device dimensions as will be explained in the following. Presently, the vast majority of integrated circuits are based on silicon, due to substantially unlimited availability, the well-understood characteristics and the experience gathered during the last 50 years, and, therefore, silicon will remain the material of choice for future circuit generations. One reason for the dominant importance of silicon in fabricating semiconductor devices is the superior characteristics of a silicon/silicon dioxide interface that allows reliable electrical insulation of different regions from each other. The silicon/silicon dioxide interface is stable at high temperatures and, thus, allows the performance of subsequent high temperature processes, as are required, for example, for anneal cycles to activate dopants and to cure crystal damage without sacrificing the electrical characteristics of the interface.
Most modern integrated circuits comprise a huge number of field effect transistors, wherein, for the reasons pointed out above, silicon dioxide is preferably used as a gate insulation layer separating a polysilicon gate electrode from a silicon channel region. In steadily improving device performance of field effect transistors, a length of this channel region has continuously been decreased to improve switching speed and drive current capability. Since the transistor performance is controlled by a voltage supplied to the gate electrode to invert the surface of the channel region to a sufficiently high charge density for providing, the desired current for a given supply voltage, a certain degree of capacitive coupling, provided by the capacitor formed by the gate electrode, the channel region and the silicon dioxide disposed therebetween, has to be maintained. It turns out that decreasing the channel length requires an increased capacitive coupling to avoid the so-called short channel behavior during transistor operation. The short channel behavior may lead to an increased leakage current and to a dependence of the threshold voltage on the channel length. Aggressively scaled transistor devices with a relatively low supply voltage and thus reduced threshold voltage may, therefore, suffer from an exponential increase of the leakage current so that the capacitive coupling of the gate electrode to the channel region has to be correspondingly increased to substantially avoid the short channel behavior. Thus, the thickness of the silicon dioxide layer has to be correspondingly decreased to provide for the required capacitance between the gate and the channel region. For example, a channel length of 0.13 μm requires a silicon dioxide thickness in the range of approximately 2-3 nm, and a gate length of 0.08 μm may require a gate dielectric made of silicon dioxide as thin as approximately 1.2 nm. Although generally high speed transistor elements having an extremely short channel may preferably be used for high speed applications, whereas transistor elements with a longer channel may be used for less critical applications, such as storage transistor elements, the relatively high leakage current caused by direct tunneling of charge carriers through an ultra thin silicon dioxide gate insulation layer may reach values for an oxide thickness in the range of 1-2 nm that are not acceptable for performance-driven circuits.
Therefore, replacing silicon dioxide as the material for gate insulation layers has been considered, particularly for extremely thin silicon dioxide gate layers. Possible alternative materials include materials that exhibit a significantly higher permittivity so that a physically higher thickness of a correspondingly formed gate insulation layer provides for a capacitive coupling that would be obtained by an extremely thin silicon dioxide layer. Commonly, a thickness required for achieving a specified capacitive coupling with silicon dioxide is referred to as capacitance equivalent thickness (CET). Thus, at a first glance, it appears that simply replacing the silicon dioxide with a high-k material is a straightforward way to obtain a capacitance equivalent thickness in the range of 1 nm and less. One approach in this respect is the introduction of nitrogen into a silicon dioxide layer to thereby increase the dielectric constant. However, reliably placing nitrogen into an extremely thin silicon dioxide layer without penetrating the underlying channel region renders this approach not very promising. Moreover, introducing nitrogen into the silicon dioxide decreases the band gap, so that for a given maximum leakage current, only a modest increase of the gate capacitance may be achieved.
It is, thus, suggested replacing silicon dioxide with high permittivity materials such as tantalum oxide (Ta2O5) with a k of approximately 25 and strontium titanium oxide (SrTiO3) having a k of approximately 150. When applying such high permittivity materials as gate dielectric, it turns out that, in addition to a plurality of problems involved in integrating the handling of these materials into well-established process sequences, the carrier mobility in the channel region is significantly affected by these high permittivity materials. Thus, although a high capacitive coupling is provided, device performance of these transistor elements is degraded by the reduced carrier mobility, thereby at least partially offsetting the advantage obtained by using the high permittivity material.
It thus appears that for the future scaling of transistor elements, a high capacitive coupling is required, wherein, on the other hand, the carrier mobility determining the drive current capability of the transistor device is not unduly negatively influenced.